1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a dynamic type semiconductor memory device operable in a self-refreshing mode.
2. Description of the Background Art
As a type of semiconductor memory devices, there is a dynamic random access memory (referred to as "DRAM" hereinafter). The DRAM includes memory cells, each of which is formed of one transistor and one capacitor and occupies a small area, and has features that high density and high integration can be facilely achieved and cost per bit is low. Therefore, the DRAMs have been widely used as memory devices having large memory capacities.
The DRAM stores information in the form of electric charges in capacitors. Therefore, periodical refreshing of data in the memory cells is required. In a conventional refreshing method, a row address strobe signal /RAS in a pulse form is externally applied at a period of about 16 .mu.s to a semiconductor memory device for refreshing the memory cell data. The row address strobe signal /RAS determines a memory cycle period of the semiconductor memory device, and also serves as a control signal which determines a timing for accepting a row address of the semiconductor memory device and a timing of an operation relating to row selection. This refreshing method is referred to as RAS only refreshing method, in which a row address is externally applied to designate a row and data of the memory cells connected to the row designated by this row address are refreshed.
A CMOS (Complementary Metal-Oxide Semiconductor) device used in the DRAM remarkably reduces power consumption and enables a battery-powered DRAM. The battery-powered DRAM is used, for example, in a portable personal computer. Battery-powered equipments such as portable personal computer use as power supplies batteries of relatively small capacities. For this reason, it is necessary to minimize the overall power consumption of a system in order to increase a battery life.
A self-refreshing mode is effective for minimizing the power consumption when only the information holding operation is carried out.
FIG. 10 is a timing chart for an external control signals in the self-refreshing mode. The self-refreshing mode is set by falling a column address strobe /CAS to "L" (at time t1) prior to fall of a row address strobe signal /RAS (at time t2). The column address strobe signal /CAS provides a timing for accepting a column address of the DRAM and a timing for controlling the column selecting operation, and further is used as a signal for determining timings for writing and reading data in a normal operation mode (during data read/write operation).
In a self-refreshing mode, a self-refreshing control circuit provided in the DRAM automatically refreshes the memory cell data as long as both the signals /RAS and /CAS are set at "L".
In this self-refreshing mode, a refreshing address, which designates a row to be refreshed, is generated by an internal address counter, and also a refreshing timing is produced by an internal timer. Therefore, it is not necessary to utilize an external circuit such as an external DRAM controller for periodically applying pulse signals for determining the refreshing timing. For this reason, power consumption of the external refreshing control circuit such as DRAM controller is not required, and the overall power consumption of the system can be reduced.
The operation mode in which the refreshing is set by setting the signal /CAS at "L" before setting the signal /RAS at "L", as described above, is generally referred to as /CAS before /RAS refreshing operation (CBR refresh). When the signal /RAS falls to "L" at time t2, the refresh is carried out in accordance with the address generated by the refreshing address counter in the DRAM.
If a time period (tRASS) in which the signal /RAS is at "L" exceeds 100 .mu.s, the DRAM carries out the refreshing in response to a refreshing request signal from the internal timer. As long as the signal /RAS is set at "L", the refreshing is repeated at a constant cycle period of, e.g., 125 .mu.s.
The self-refreshing is completed by raising the signal /RAS to "H" at time t4.
FIG. 11 shows an overall construction of a DRAM having the self-refreshing function. In FIG. 11, the DRAM2 includes a memory cell array 100 having dynamic type memory cells disposed in a matrix of rows and columns, a row decoder 102 which decodes an internal row address signal RA to select a corresponding row in the memory cell array 100, a sense amplifier group 104 which senses and amplifies data of memory cells connected to the selected row in the memory cell array 100, a column decoder 106 which decodes an applied internal column address signal CA to generate a column selecting signal for selecting the corresponding column in the memory cell array 100, and an IO gate 108 which connects the selected column in the memory cell array 100 to an internal data line 110 in response to the column selecting signal supplied from the column decoder 106.
The sense amplifier group 104 includes sense amplifiers disposed correspondingly to the respective columns in the memory cell array 100. The DRAM further includes a multiplexer 112 which selectively allows passage of an externally applied address signal A and a refreshing address REFA supplied from an address counter 120, a row address buffer 114 which receives a signal from the multiplexer 112 to generate the internal row address signal RA, a column address buffer 116 which receives the externally applied address signal A to generate the internal column address signal CA, a refreshing control circuit 118 which receives the externally applied row address strobe signal /RAS and column address strobe signal /CAS and generates various control signals required for the refreshing when the refreshing mode is instructed, an RAS control signal generating circuit 122 which generates signals for controlling circuits related to the signal RAS in response to the row address strobe signal /RAS and the control signal supplied from the refreshing control circuit 118, and a CAS control signal generating circuit 124 which generates signals for controlling circuits related to the signal CAS in response to the column address strobe signal /CAS and the control signal supplied from the RAS control signal generating circuit 122.
The control signal supplied from the RAS control signal generating circuit 122 is applied to the row decoder 102 and row address buffer 114 to determine the operation timings of them, and also determines the operation timing of the sense amplifier group 104 (the signal path is not shown). The circuits related to the signal RAS include circuitry related to the row selection and circuitry related to the sensing operation. The control signal supplied from the CAS control signal generating circuit 124 determines the operation timings of the column decoder 106 and column address buffer 116, and also determines operations for externally writing and reading data, as will be described later. The CAS control signal generating circuit 124 is active while the RAS control signal generating circuit 122 is generating the internal RAS signal, and the DRAM is in the active state and is carrying out the row selecting operation.
The DRAM further includes a timer 126, which is activated in response to a refreshing instruction supplied from the refreshing control circuit 118 and generates the refreshing request signals at intervals of a predetermined time, an address counter 120 which carries out a counting operation under the control of the refreshing control circuit 118, a write control circuit 128, which generates the internal write signal for determining the data write timing in response to the control signal supplied from the CAS control signal generating circuit 124 and the externally applied write enable signal /WE, an input circuit 130 which produces internal write data from externally applied write data D and transmits the same to a selected memory cell in the memory cell array 100 in response to the internal write signal supplied from the write control circuit 128, and an output circuit 130 which produces external read data Q from the data of a selected memory cell in the memory cell array 100 in response to the control signal supplied from the CAS control signal generating circuit 124.
The write control circuit 128 produces the internal write signal in response to later one of the fallings of the column address strobe signal /CAS and write enable signal /WE. The output circuit 132 is activated in response to the fall of the column address strobe signal /CAS.
In FIG. 11, an address buffer 140 includes the row address buffer 114 and the column address buffer 116, of which address accepting timings are determined by the control signals supplied from the RAS control signal generating circuit 122 and the CAS control signal generating circuit 124, respectively. In these operations, the external address signal A may be formed of the row address signal and column address signal applied in a time-division multiplexed manner or may be in a nonmultiplexed manner. The input circuit 130 and the output circuit 132 may carry out the input and output of data through separate pin terminals or common pin terminals. Then, an operation of the DRAM shown in FIG. 11 will be described below in brief.
In the normal operations for writing and reading of data, the multiplexer 112 applies the external address signal A to the row address buffer 114. When the row address strobe signal /RAS falls to "L", the DRAM is activated and the memory cycle starts. The RAS control signal generating circuit 122 generates the internal control signal to the row address buffer 114 in response to the fall of the signal /RAS. The row address buffer 114 responds to the applied control signal by producing an internal row address signal RA from the address signal A received through the multiplexer 112, to the row decoder 102. The row decoder 102 responds to the control signal applied from the RAS control signal generating circuit 122 by decoding the internal row address signal RA and selecting the corresponding row in the memory cell array 100. Then, the sense amplifier group 104 is activated by the control signal (not shown) applied from the RAS control signal generating circuit 122, and the data of the memory cells connected to the selected row is sensed, amplified and latched.
When the column address strobe signal /CAS falls to "L", the column address buffer 116 takes in the external address signal A and generates an internal column address signal CA under the control by the CAS control signal generating circuit 124. Then, the column decoder 106 decodes the internal column address signal CA to select a corresponding column in the memory cell array 100, and the selected column is connected through the IO gate 108 to the internal data line 110.
In the data writing operation, the write enable signal /WE is in the active state of "L", and the write control circuit 128 generates the internal write signal when the signal /CAS and the signal /WE both attain "L". The input circuit 130 produces an internal write data from an external write data D in accordance with the internal write signal supplied from the write control circuit 128. Thereby, the data is written in the memory cell located at the crossing of the column and row selected by the column decoder 106 and row decoder 102.
In the data read operation, the output circuit 132 produces an external read data Q from the data read to the internal data line 110 under the control by the CAS control signal generating circuit 124.
In the refreshing operation mode, the refreshing control circuit 118 is activated. When the refreshing control circuit 118 detects the designation of the self-refreshing mode in accordance with the combination of the states of the signals /RAS and /CAS, it applies a switching signal to the multiplexer 112 and enables the address counter 120. The address counter 120 in the normal operation mode latches the count.
The refreshing control circuit 118 also activates the timer 126, and applies a control signal to the RAS control signal generating circuit 122 for activating the RAS control signal generating circuit 122. Responsively, the RAS control signal generating circuit 122 generates the control signal, and the row address buffer 114 generates the internal row address signal RA from the refreshing address REFA received through the multiplexer 112 from the address counter 120, and applies the signal RA to the row decoder 102. The row decoder 102 decodes the internal row address signal RA produced from the refreshing address REFA to select a corresponding row in the memory cell array 100. The sense amplifier group 104 is activated under the control of the RAS control signal generating circuit 122 to sense and amplify the data of the memory cells connected to the selected row.
The operation of the CAS control signal generating circuit 124 is inhibited under the control of the RAS control signal generating circuit 122 even when the signal /CAS is set at "L". Thereby, the operations of the column address buffer 116, column decoder 106, write control circuit 128 and output circuit 132 are inhibited. The internal control signal supplied from the RAS control signal generating circuit 122 is maintained only for a predetermined period under the control of the refreshing control circuit 118, and all the control signals supplied from the RAS control signal generating circuit 122 are deactivated upon expiration of this refreshing period. Thereby, data of the memory cells which are sensed, amplified and latched by the sense amplifier group 104 are restored in the memory cells, and the DRAM returns to the precharge state.
Then, upon detection of the elapsing of the predetermined time period, the timer 126 applies the refreshing request signal to the refreshing control circuit 118. The refreshing control circuit 118 activates the RAS control signal generating circuit 122 again in response to the refreshing request signal. The count of the address counter 120 was incremented or decremented by one in response to a count instructing signal, which in turn was supplied from the RAS control signal generating circuit 122 when the last refreshing operation was completed. Therefore, in the current refreshing cycle, the address counter 120 generates the refreshing address REFA which designates the next row. In accordance with this refreshing address REFA, the row selecting operation and the refreshing of the data of the memory cells are carried out. Thereafter, the refreshing operations are carried out at intervals of the predetermined time period while the signals /RAS and /CAS are at "L". When the signal /RAS rises to "H", the refreshing control circuit 118 resets the timer 126 and sets the multiplexer 112 at the state for selecting the external address signal A. Also, the refreshing control circuit 118 sets the address counter 120 in the latch state after changing its count by one after the completion of the refreshing operation. Further, the refreshing control circuit 118 is released from the refreshing control operation by the rise of the signal /RAS to "H".
As described above, by continuously setting the signals /RAS and /CAS at "L" at the predetermined timing relationship, the data of the memory cells are automatically and internally refreshed.
FIG. 12 shows specific constructions of the refresh control circuit, RAS control signal generating circuit and CAS control signal generating circuit shown in FIG. 11. In FIG. 12, the refreshing control circuit 118 includes a CBR detecting circuit 1 which is responsive to the signals /RAS and /CAS to generate an internal refreshing instructing signal CBR indicating whether the self-refreshing mode is designated or not, a set /reset flip-flop (referred to merely as "RS flip-flop" hereinafter) 2 which is set in response to the signal CBR from the CBR detecting circuit 1 and is reset in accordance with the signal /RAS, a pulse generating circuit 3 which is activated by an output Q of the RS flip-flop 2 and generates a one-shot pulse in response to the signal /RAS, an OR circuit 4 which receives a refreshing request signal .phi.REF from the timer 126 and the output of the pulse generating circuit 3, and a one-shot pulse generating circuit 5 which is responsive to the output of the OR circuit 4 to generate a one-shot pulse signal PU.
The CBR detecting circuit 1 includes an inverter circuit 12 for inverting the column address strobe signal /CAS, and an AND circuit 14 for receiving the output of the inverter circuit 12 and the row address strobe signal /RAS. The AND circuit 14 generates the signal at "H" when both the inputs attain "H" level. The RS flip-flop 2 goes to the set state in response to the rise of the internal refreshing mode instructing signal CBR to "H", and supplies the signal at "H" through its output Q. Also, the RS flip-flop 2 goes to the reset state in response to the rise of the signal /RAS to "H" and resets its output Q at "L". An output /Q of the RAS flip-flop 2 is used as a control signal of the selecting operation of the multiplexer 112. The OR circuit 4 supplies a signal at "H" when one of the inputs attains "H". The one-shot pulse generating circuit 5 is responsive to the rise of the output signal from the OR circuit 4 to generate the pulse signals PU having a predetermined time width (a time width normally including a time period from the starting of a row selecting operation to the completion of the sense and latch operations of the sense amplifier).
The RAS control signal generating circuit 122 includes an NOR circuit 20 for receiving the row address strobe signal /RAS as well as the signal from the output Q of the RS flip-flop 2, an OR circuit 22 for receiving an output of the NOR circuit 20 and an output of the one-shot pulse generating circuit 5, and an RAS-related control circuit 24 which is responsive to the output of the OR circuit 22 to generate a signal for controlling the circuit related to the signal RAS. The NOR circuit generates the signal at "L" when at least one of the inputs attains "H".
The CAS control signal generating circuit 124 includes an RS flip-flop 32 which is set in response to the internal refreshing instructing signal CBR and is reset in response to the column address strobe signal /CAS, a three-input NOR circuit 34 which receives a signal CCE supplied from the output Q of the RS flip-flop 32 as well as the row address strobe signal /RAS and the column address strobe signal CAS, and a CAS-related control circuit 30 which is responsive to the output of the NOR circuit 34 to generate signals for controlling the circuit(s) related to the signal CAS.
Now, an operation of the self-refreshing control circuitry shown in FIG. 12 will be described with reference to FIG. 13 showing operation waveforms in the self-refreshing operation.
If the signals /RAS and /CAS are asserted at the timings along the /CAS before /RAS relationship, the signal CBR supplied from the CBR detecting circuit 1 rises to "H". The internal refreshing instructing signal CBR falls to "L" in response to the fall of the row address strobe signal /RAS. The RS flip-flop 2, which is set in response to the rise of the signal CBR, activates the timer 126 and inhibits the row selecting operation along the row address strobe signal /RAS through the NOR circuit 20.
Then, in response to the fall of the row address strobe signal /RAS, the output of the pulse generating circuit 3 rises and attains "H" for a predetermined time period, and the output of the OR circuit 4 rises to "H". The one-shot pulse generating circuit 5 responds to the output of the OR circuit 4 by generating the signal PU at "H" for a predetermined time period. Responsively, the OR circuit 22 generates an internal RAS signal .phi.RAS, and the RAS-related control circuit 24 carries out the control operation relating to the row selection and the like in accordance with the internal RAS signal .phi.RAS. During this operation, the outputs /Q of the RS flip-flop 2 are being applied to the multiplexer 112, and thereby the multiplexer 112 changes its connection path so as to apply the refreshing address supplied from the address counter 120 to the row address buffer 114.
Meanwhile, the RS flip-flop 32, which is set in response to the internal refreshing instructing signal CBR, supplies the output Q at "H", and the output of the NOR circuit 34 attains "L". While the output signal CCE supplied from the RS flip-flop 32 is at "H", the internal CAS signal .phi.CAS is set at "L". Thereby, in the self-refreshing mode, the erroneous write and read of the data, which may be caused, e.g., by a noise on the control signal /CAS, is inhibited.
After the elapsing of the predetermined time period, the timer 126 generates the refreshing request signal .phi.REF. Thereby, the internal RAS signal .phi.RAS having the pulse width corresponding to the pulse signal PU is generated through the OR circuit 4, one-shot pulse generating circuit 5 and OR circuit 22, and the refreshing operation is carried out again. After the completion of the refreshing operation, the RAS-related control circuit 24 increments or decrements by one the count of the counter 120.
Thereafter, the refreshing is carried out each time the timer 126 generates the refreshing request signal .phi.REF at the intervals of the predetermined time period.
When the row address strobe signal /RAS rises to "H", the RAS flip-flop 2 is reset and supplies the signal at the "L" level through its output Q. Thereby, the timer 126 is reset, and the multiplexer 112 goes to the state for selecting an external address. The counter 120 goes to the state for latching the count in accordance with the output of the RS flip-flop 2 (path for this is not shown in the figure).
When the signal /RAS rises, the self-refreshing may be under execution in accordance with the refreshing request signal .phi.REF supplied from the timer 126, because it is impossible to externally determine the stage to which the self-refreshing proceeds. Even if the signal /RAS rises to "H", the self-refreshing is carried out in accordance with the internal RAS signal .phi.RAS as far as the internal RAS signal .phi.RAS is generated. For this reason, it is generally necessary to maintain the signal /RAS at "H" for a time period of at least one cycle, in a case that the signal /RAS is fallen to "L" for changing the self-refreshing mode to the normal operation mode.
The RS flip-flop 32 is provided for preventing the erroneous write and read of data, which may be caused by the generation of the internal CAS signal .phi.CAS in the self-refreshing mode. The RS flip-flop 32 is not essential for merely preventing the generation of the internal signal .phi.CAS. Application of signal of the output Q of the RS flip-flop 2 directly to the NOR circuit 34 may accomplish such prevention. Why RS flip-flop 32 which is reset in response to the column address strobe signal /CAS is provided and the signal /CAS is also applied to the NOR circuit 34 is as follows.
In the self-refreshing mode, the refreshing address counter 120 generates the refreshing address. For the periodical refreshing of the memory cells in each row in the memory cell array in the DRAM, it is necessary to operate the refreshing address counter correctly and to generate the refreshing address periodically. If refreshing address counter 120 is a ten-bit counter, the counter is required to generate the same refreshing address every 1024 cycles.
As one of test modes of the DRAM, there is a counter check operation for checking whether the refreshing address counter 120 operates correctly or not. Now, the counter check operation will be described with reference to an operation waveform diagram of FIG. 14.
As described above, the refreshing address counter 120 is a ten-bit counter. Initially, the data of, e.g., "1" is written into the DRAM, with the column address fixed and with the row address successively incremented by one. The write of data is carried out in accordance with the normal data write operation mode. Specifically, the write of data is carried out by falling the signal /CAS and the signal /WE after the fall of the signal /RAS.
Then, the data written in the respective bits in the 1024 rows is changed into the data "0". For this change, the operation shown in FIG. 14 is carried out. Specifically, the DRAM is set at the self-refreshing (CBR refreshing) mode along the /CAS before /RAS timing relationship. Thereby, the RS flip-flop 32 shown in FIG. 12 is set, and the signal CCE rises to "H". At time t2', the column address strobe signal /CAS rises to "H". Thereby, the circuit(s) (not shown) related to the signal /CAS (i.e., circuitry directly receiving the column address strobe signal /CAS) is initialized.
In response to the rise of the signal /CAS to "H", the RS flip-flop 32 is reset and the signal CCE falls to "L".
At time t2", the signal /CAS falls, and responsively the output signal .phi.CAS of the NOR circuit 34 shown in FIG. 12 rises to "H", so that the CAS-related circuitry enters the operating state. This enables the write or read of data to the DRAM. FIG. 14 shows the operation waveform in an early write mode in which the write enable signal /WE falls to "L" prior to the fall of the column address strobe signal /CAS. In this case, the external address signal A is taken into the column address buffer 116 at time t2", and the internal column address signal CA is generated, so that the operation for selecting the column in the memory cell array is carried out. Before time t2", a row has been selected in accordance with the refreshing address REFA from the refreshing address counter.
At time t2", the column address is decided, and the write control circuit 128 shown in FIG. 11 is activated, so that the internal write signal is generated. Responsively, an input circuit 130 accepts the external write data D of "0", and produces the internal write data which is transmitted to the internal data line 110. Thereby, the data is written in the memory cell located at the crossing of the row designated by the refreshing address and the column designated by the external column address signal. The operation shown in FIG. 14 is repeated 1024 times. Thereby, the data of all the memory cells of the same column in the 1024 rows (i.e., of the column address same as the column address used for the write of "1") changes to "0".
Then, the DRAM is set in the self-refreshing mode along the timing relationship of the /CAS before /RAS again, and the counter 120 is set in the operating state. The signal /CAS is raised to "H" again, and then is fallen, to "L" at the time t2". In this operation, the signal /WE is set at "H", whereby the data is read from the column corresponding to the applied external address in response to the fall of the column address strobe signal /CAS. This read operation is similarly repeated 1024 times. If all the data thus read is "0", it is determined that the address counter 120 operates correctly.
The refreshing address counter 120 is operated 1024 times because the initial value of the refreshing address counter 120 is set at an arbitrary value in a dummy cycle carried out upon initialization of DRAM.
The pulse signal PU generated from the one-shot pulse generating circuit 5 in the self-refreshing mode is made to have a time length nearly equal to the cycle time required for the normal write and read of the data. In a case of the CBR refreshing carrying out only one refreshing operation (in which only the refreshing address counter is used without using the timer), the duration in which the signal /RAS is at "L" is set at up to about 10 .mu.s. The maximum duration for the active state of the signal /RAS in one cycle period is determined so as to prevent the reduction of the word line potential, which may be caused by leak and may impair correct write/read of data.
As described above, the self-refreshing mode enables the refreshing to be internally executed by the DRAM without an operation of an external control circuit of the DRAM, so that the power consumption of the system can be reduced.
The self-refreshing mode is set, as shown in FIG. 10, by falling the signal /CAS to "L" at time t1 and then falling the signal /RAS to "L". When the duration. tRASS of the "L" state of the signal /RAS equals 100 .mu.s or more, the internal refreshing is executed under the control of the timer.
In order to return from the operation in the self-refreshing mode to the normal operation mode, both the signals /RAS and /CAS must be raised to "H", because all the circuits related to the signals RAS and CAS must be brought to the precharge state. For the restoration to the initial state, specification values for various signals such as a set-up time and a hold time are generally determined in order to ensure the correct memory operation by the precharge of a signal line and correct determination of the signal state.
The column address strobe signal /CAS generally rises to "H" after the rise of the row address strobe signal /RAS. However, as shown in FIG. 10, it is permitted that the column address strobe signal /CAS may rise to "H" prior to rise of the signal /RAS. In this case, however, it is required to set a CAS preceding time tCHS at 50 ns or less for ensuring the correct operation in DRAM specification.
The time difference tCHS of 50ns or less between the times t3 and t4 is extremely shorter than the duration tRASS of 100 .mu.s in which the signal /RAS maintains "L" in the self-refreshing mode. Therefore, the above condition requires extremely severe restriction on the timing design of the memory system. As a method for mitigating the condition requiring 50 ns or less, it may be envisaged that the "L" state of the column address strobe signal /CAS is latched at the time (t2) of the fall of the row address strobe signal /RAS and this latch state is reset by the signal /RAS.
For this purpose, for example, a latch circuit which is activated in response to the signal CBR and latches the signal /CAS in response to the row address strobe signal /RAS can be provided, and the output of this latch circuit can be used in place of the column address strobe signal /CAS shown in FIG. 12. In this case, when the signal CBR or the signal /RAS is inactive, this latch circuit must attain a through state for allowing passage of the column address strobe signal /CAS as received. However, if such latch circuit is used, the internal signal CAS is reset by the external signal /RAS, so that the counter check operation, which has been described with reference to FIG. 14, cannot be executed.
Therefore, such latch circuit cannot be used if the counter check function is required.
On the other hand, if the condition that the CAS preceding time tCHS is 50 ns or less is not satisfied, following disadvantages may be caused. In the self-refreshing mode, if the signal /RAS is in the "L" state for 100 .mu.s, the timer operates to generate the refreshing request .phi.REF. In this case, however, an operating margin has been taken into account, and thus the timer may be activated even when the row address strobe signal /RAS maintains "L" for 90 .mu.s.
Now, consideration will be made on a state that the timer generates the refreshing request signal .phi.REF if the signal /RAS maintains "L" for 90 .mu.s in the DRAM, as shown in FIG. 15. It is assumed that, in the self-refreshing operation mode, the column address strobe signal /CAS rises to "H" at time t2' and then falls to "L" at time tA. In this state, the DRAM generates the internal RAS signal .phi.RAS, and the row selection and the refreshing operation are carried out in the DRAM array. In this state, when the signal /CAS falls to "L" at time tA, the column selecting operation is carried out in accordance with the external address signal and the data is written in or read from the selected memory cells. In FIG. 15, data in a "don't care" state is regarded as a valid data Da.
In general, erroneous write and read of data into and from the memory cells which are being refreshed are prevented by inhibiting generation of the internal CAS signal .phi.CAS in the self-refreshing operation mode. However, if the counter check function is provided, the internal CAS signal .phi.CAS is generated in accordance with the externally applied column address strobe signal /CAS, so that the write or read of data is carried out during the self-refreshing operations.
In general, since it is impossible to externally recognize the progress state of the refreshing in the self-refreshing operation mode, the self-refreshing mode is generally used in the standby state and is carried out only for the data holding. Therefore, the external signals are preferably maintained at a fixed state in view of the low power consumption.
However, depending on the actual conditions of practical use, the external column address strobe signal /CAS may temporarily rise to "H" and then fall to "L". Therefore, it is preferable to provide means for preventing erroneous write and read of data in the self-refreshing mode for mitigating the restriction on the use of the DRAM.
In the design of the timing of the system, it is preferable to prevent erroneous write and read of data and to minimize the restriction on the preceding time tCHS of the column address strobe signal /CAS in the self-refreshing mode. In other words, the time duration of "don't care" state of the signal /CAS should be made as long as possible in view of a timing design and usability, as shown in FIG. 16.